A paper in 1989 [Lage89] first noted the fact that integrated circuits (IC) have a growing proportion of power and ground pins as a fraction of their total pin counts, and that Boundary-Scan technology [IEEE01] did not address testing for open-pin defects on these pins. The paper made some proposals for adding testability to such devices and making such defects observable in the Boundary Register, but the ideas did not gain traction.
Ver artigo original em: http://literature.cdn.keysight.com/litweb/pdf/5990-3303EN.pdf
Boundary Scan Keysight
Manufacturing Test Solutions for DDR Memory